New vector instructions provided by the Intel® Xeon PhiTM Coprocessor Instruction Set utilize a dedicated 512-bit wide vector floating-point unit (VPU)
that is provided for each of the cores.

The Vector Processor Unit includes the EMU (extended math unit) and executes (one of):
- 16 integer operations (32-bit),
- 16 floating point operations (single-precision),
- 8 floating-point operations (double-precision),
per clock cycle.

Each operation can be a floating-point multiply-add, giving 32 single precision floating-point operations per cycle.

The VPU contains the vector register file (32 registers per thread context),
and can read one of its operands directly from memory, including data format conversion on the fly.
Broadcast and swizzle instructions are also available.

The EMU can perform base-2 exponential, base-2 logarithm, reciprocal, and reciprocal square root of single precision floating-point values.

Если пытаться использовать код с такими инструкциями на обычном процессоре, то будет #UD исключение, сообщающее о недопустимой инструкции.

A full list of the instructions supported by the Intel® Xeon PhiTM coprocessor can be found in the document (Reference Number: 327364)
"Intel® Xeon PhiTM Coprocessor Instruction Set Architecture Reference Manual".

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